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ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
PRODUCT OVERVIEW
The ADCDS-1403 is an application-specific video signal processor designed for electronicimaging applications that employ CCD's (charge coupled devices) as their photodetector. The ADCDS-1403 incorporates a "user configurable" input amplifier, a CDS (correlated double sampler) and a sampling A/D converter in a single package, providing the user with a complete, high performance, low-cost, low-power, integrated solution. The key to the ADCDS-1403's performance is a unique, high-speed, high-accuracy CDS circuit, which eliminates the effects of residual charge,
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 INPUT/OUTPUT CONNECTIONS Function Pin FINE GAIN ADJUST OFFSET ADJUST DIRECT INPUT INVERTING INPUT NON-INVERTING INPUT +2.4V REF. OUTPUT ANALOG GROUND NO CONNECT NO CONNECT BIT 14 (LSB) BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4
+12VA 39 759 5239 25 START CONVERT 1 FINE GAIN ADJUST -5VA 38
FEATURES
14-bit resolution 3MPPS throughput rate (14-bits) Functionally complete Very low noise Excellent Signal-to-Noise ratio Edge triggered Small, 40-pin, TDIP package Low power, 500mW typical Low cost Programmable Analog Bandwidth
charge injection and "kT/C" noise on the CCD's output floating capacitor, producing a "valid video" output signal. The ADCDS-1403 digitizes this resultant "valid video" signal using a high-speed, low-noise sampling A/D converter. The ADCDS-1403 requires only the rising edge of start convert pulse to initiate its conversion process. Additional features of the ADCDS-1403 include gain adjust, offset adjust, precision +2.4V reference, and a programmable analog bandwidth function.
Function
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
+5VA 36
NO CONNECT +12V -5VA ANALOG GROUND +5VA ANALOG GROUND +5VD DIGITAL GROUND DIGITAL GROUND A1 AO NO CONNECT NO CONNECT DATA VALID REFERENCE HOLD START CONVERT OUT-OF-RANGE BIT 1 (MSB) BIT 2 BIT 3
+5VD 34
INVERTING INPUT 4 INPUT AMPLIFIER 0.01F DIRECT INPUT 3 NON-INVERTING INPUT 5 5K 9 CORRELATED DOUBLE SAMPLER
23 BIT 1 (MSB) SAMPLING A/D 10 BIT 14 (LSB)
OFFSET ADJUST 2
REFERENCE HOLD 26
TIMING AND CONTROL
24 OUT-OF-RANGE 6 +2.4V REFERENCE OUTPUT
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32, 33 DIGITAL GROUND
27 DATA VALID
30 31 AO A1
7, 35, 37 ANALOG GROUND
Figure 1. ADCDS-1403 Functional Block Diagram
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MDA_ADCDS-1403.B01 Page 1 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
ABSOLUTE MAXIMUM RATINGS PARAMETERS
+12V Supply (Pin 32) -5V Supply (Pin 38) +5V Supply (Pin 34, 36) Digital Input (Pin 25, 26, 30, 31) Analog Input (Pin 3,4,5) Lead Temperature (10 seconds)
DYNAMIC PERFORMANCE MAX.
+14 +0.3 +6.5 Vdd+0.3V +6 300
MIN.
100 -- --
TYP.
-- 25 100
MAX.
-- -- --
UNITS
ns mV/us mV/us
MIN.
0 -6.5 -0.3 -0.3 -6 --
TYP.
-- -- -- -- -- --
UNITS
Volts Volts Volts Volts Volts C
Reference Hold Aquisition Time Droop @ +25C @ -55 to +125C Peak Harmonic (SFDR) (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Peak Harmonic (SFDR) (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Total Harmonic Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Signal-to-Noise Ratio Without Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C Signal-to-Noise Ratio With Distortion (CDD-IN, input on pin (3) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C (Input on pin (5) Input @ 98kHz) @ +25 C @ 0 to +70C @ -55 to +125C
Functional Specifications
The following specifications apply over the operating temperature range, under the following conditions: Vcc=+12V, +Vdd=+5V, Vee=-5V, fin=98KHz, sample rate=3MHz.
-- -- --
-76 -76 -74
-- -- --
dB dB dB
ANALOG INPUT
Input Voltage Range (externally configurable) Input Resistance Input Capacitance
MIN.
0.350 -- --
TYP.
2.8 5000 10
MAX.
-- -- --
UNITS
Volts p-p Ohm pF
DIGITAL INPUTS
Logic Level Logic 1 Logic 0 Logic Loading Logic 1 Logic 0 +3.5 -- -- -- -- -- -- -- -- +.80 +10 -10 Volts Volts uA uA
-- -- --
-76 -76 -74
-- -- --
dB dB dB
-- -- --
-75 -75 -74
-- -- --
dB dB dB
DIGITAL OUTPUTS
Logic Levels Logic 1 (IOH = .5ma) Logic 1 (IOH = 50a) Logic 0 (IOL = 1.6ma) Logic 0 (IOL = 50ua) Internal Reference Voltage (Fine gain adjust pin (1) grounded) +25C 0 to 70C -55 to +125C External Current Differential Nonlinearity (Histogram, 98kHz) +25C 0 to 70C -55 to +125C Integral Nonlinearity +25C 0 to 70C -55 to +125C Guaranteed No Missing Codes 0 to 70C -55 to +125C DC Noise +25C 0 to 70C -55 to +125C Offset Error +25C 0 to 70C -55 to +125C Gain Error +25C 0 to 70C -55 to +125C +2.4 +4.5 -- -- -- -- -- -- -- -- +0.4 +0.1 Volts Volts Volts Volts
-- -- --
-76 -76 -74
-- -- --
dB dB dB
2.35 2.35 2.35 --
2.4 2.4 2.4 1.0
2.45 2.45 2.45 --
Volts Volts Volts mA
73 73 70
75 75 73
-- -- --
dB dB dB
STATIC PERFORMANCE
-0.90 -0.90 -1.0 -- -- -- 14 14 -- -- -- -- -- -- -- -- -- 0.5 0.5 0.6 2.5 2.5 2.5 -- -- 1.0 1.0 1.25 0.6 0.6 0.6 1.00 1.35 1.35 +.90 +.90 +1.0 -- -- -- -- -- 1.6 2.0 2.5 1.25 1.25 1.45 2.8 2.8 2.8 LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB %FSR %FSR %FSR %FSR %FSR %FSR
73 73 70
75 75 73
-- -- --
dB dB dB
-- -- --
71 71 70
-- -- --
dB dB dB
-- -- --
71 71 70
-- -- --
dB dB dB
SIGNAL TIMING
Conversion Rate -55 to +125C Conversion Time Start Convert Pulse Width Power Supply Range +12V Supply +5V Supply -5V Supply 3 -- 20 -- 200 150 -- -- -- MHz nsec nsec
POWER REQUIREMENTS
+11.4 +4.75 -4.75 +12.0 +5.0 -5.0 +12.6 +5.25 -5.25 Volts Volts Volts
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MDA_ADCDS-1403.B01 Page 2 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
POWER REQUIREMENTS
Power Supply Current +12V Supply Power Supply Current +5V Supply -5V Supply Power Dissipation Power Supply Rejection (5%) @ +25C
MIN.
-- -- -- -- --
TYP.
+13 +40 -27 0.50 0.02
MAX.
+16 +46 -35 0.60 0.03
UNITS
mA mA mA Watts %FSR/%V
Direct Mode (AC Coupled)
This is the most common input configuration as it allows the ADCDS1403 to interface directly to the output of the CCD with a minimum amount of analog "front-end" circuitry. This mode of operation is used with fullscale video input signals from 0.350Vp-p to 2.8Vp-p. Figure 2a. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. The coarse gain of the input amplifier is determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1% tolerance. Additional fine gain adjustment can be accomplished using the Fine Gain Adjust (pin 1 see Figure 5). Figure 2b. describes the typical configuration for applications using a video input signal with an amplitude greater than 0.350Vp-p and less than 2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1403 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the input amplifier can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance.
ENVIRONMENTAL
Operating Temperature Range ADCDS-1403 ADCDS-1403EX Storage Temperature Package Type Weight 0 -55 -65 -- -- -- 40-pin, TDIP 16.10 grams +70 +125 +150 C C C
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADCDS-1403 requires careful attention to pc-card layout and power supply decoupling. The device's analog and digital grounds are connected to each other internally. Depending on the level of digital switching noise in the overall CCD system, the performance of the ADCDS-1403 may be improved by connecting all ground pins (7,32,33,35, 37) to a large analog ground plane beneath the package. The use of a single +5V analog supply for both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial. 2. Bypass all power supplies to ground with a 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor. Locate the capacitors as close to the package as possible. 3. If using the suggested offset and gain adjust circuits (Figure 3 & 5), place them as close to the ADCDS-1403's package as possible. 4. A0 and A1 (pins 30, 31) should be bypassed with 0.1f capacitors to ground to reduce susceptibility to noise.
4
759
5239
VIN NO CONNECT
3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2a.
Rext 4 759 5239
ADCDS-1403 Modes of Operation
The input amplifier stage of the ADCDS-1403 provides the designer with a tremendous amount of flexibility. The architecture of the ADCDS1403 allows its input-amplifier to be configured in any of the following configurations: * Direct Mode (AC coupled) * Non-Inverting Mode * Inverting Mode When applying inputs which are less than 2.8Vp-p, a coarse gain adjustment (applying an external resistor to pin 4) must be performed to ensure that the full scale video input signal (saturated signal) produces a 2.8Vp-p signal at the input-amplifier's output (Vout). In all three modes of operation, the video portion of the signal at the CDS input (i.e. input-amplifier's Vout) must be more negative than its associated reference level and Vout should not exceed 2.8V DC. The ADCDS-1403 achieves it specified accuracies without the need for external calibration. If required, the device's small initial offset and gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and OFFSET ADJUST (pin 2) features.
VIN NO CONNECT 3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2b.
Rext 759 5239
4
NO CONNECT VIN
3 5
0.01F VOUT = 2.8Vp-p
5k9
Figure 2c.
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MDA_ADCDS-1403.B01 Page 3 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Non-Inverting Mode
The non-inverting mode of the ADCDS-1403 allows the designer to either attenuate or add non-inverting gain to the video input signal. This configuration also allows bypassing the ADCDS-1403's internal coupling capacitor, allowing the user to provide an external capacitor of appropriate value. Figure 2c. describes the typical configuration for applications using video input signals with amplitudes greater than 0.350Vp-p and less than 2.8Vp-p (with common mode limit of 2.5V DC). Using a single external series resistor (see Figure 4.), the coarse gain of the ADCDS-1403 can be set with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of the circuit can be determined from the following equation: VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having a 1% tolerance. Figure 2d. describes the typical configuration for applications using a video input signal whose amplitude is greater than 2.8Vp-p. Using a single external series resistor (Rext 1) in conjunction with the internal 5K (1%) resistor to ground, an attenuation of the input signal can be achieved. Additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]* [1+(523/(75+Rext2))], with all internal resistors having a 1% tolerance.
Rext2 4 759 5239
Inverting Mode
The inverting mode of operation can be used in applications where the analog input to the ADCDS-1403 has a video input signal whose amplitude is more positive than its associated reference level. The ADCDS-1403's correlated double sampler (i.e. input amplifier's VOUT) requires that the video signal's amplitude be more negative than its reference level at all times (see timing diagram for details). Using the ADCDS-1403 in the inverting mode allows the designer to perform an additional signal inversion to correct for any analog "front end" pre-processing that may have occurred prior to the ADCDS-1403. Figure 2e. describes the typical configuration for applications using a video input signal with a maximum amplitude of 0.350Vp-p. Additional fine gain adjustments can be made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = -VIN*(523/75), with all internal resistors having a 1% tolerance. Figure 2f. describes the typical configuration used in applications needing to invert video input signals whose amplitude is greater than 0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial gain of the ADCDS-1403 can be set, with additional fine gain adjustments being made using the Fine Gain Adjust function (pin 1). The coarse gain of this circuit can be determined from the following equation: VOUT = 2.8Vp-p = -VIN*(523/75+Rext), with all internal resistors having a 1% tolerance.
ADCDS-1403
3 NO CONNECT Rext1 VIN 5 5k9 0.01F VOUT = 2.8Vp-p
+5V
External Series Resistor
20K9
Offset Adjust 2
Figure 2d.
-VIN 4 759 5239
-5V
3 NO CONNECT 5
0.01f VOUT = 2.8Vp-p
Figure 3. Offset Adjustment Circuit
Coarse Gain Adjustment Plot External Gain Resistor vs. Full Scale Video Input
5k9
External Gain Resistor (Ohms)
10000
Direct Mode & Non-Inverting Mode
Figure 2e.
Rext -VIN 4 759 5239
1000
Inverting Mode
3 NO CONNECT 5
0.01f VOUT = 2.8Vp-p
100
5k9
10 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 Full Scale Video Signal (Volts)
Figure 4. Coarse Gain Adjustment Plot Figure 2f.
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MDA_ADCDS-1403.B01 Page 4 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Offset Adjustment
Manual offset adjustment for the ADCDS-1403 can be accomplished using the adjustment circuit shown in Figure 3. A software controlled D/A converter can be substituted for the 20K: potentiometer. The offset adjustment feature allows the user to adjust the Offset/Dark Current level of the ADCDS-1403 until the output bits are 00 0000 0000 0000 and the LSB flickers between 0 and 1. Offset adjust should be performed before gain adjust to avoid interaction. The ADCDS-1403's offset adjustment is dependent on the value of the external series resistor used in the offset adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates the typical relationship between the external series resistor value and its offset adjustment capability utilizing 5V supplies.
For Example: External 50K resistor:
10mV of noise or voltage variation at the potentiometer will produce 0.25LSB's of output variation. 2. 100mV of noise or voltage variation at the potentiometer will produce 2.5LSB's of output variation. The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset adjustment sensitivity over a wide range of external resistor and noise values. If a large offset voltage is required, it is recommended that a very low noise external reference be used in the offset adjust circuit in place of power supplies. The ADCDS-1403's +2.4V reference output could be configured to provide the reference voltage for this type of application. 1.
Offset Adjustment Sensitivity
It should be noted that with increasing amounts of offset adjustment (smaller values of external series resistors), the ADCDS-1403 becomes more susceptible to power supply noise or voltage variations seen at the wiper of the offset potentiometer.
Fine Gain Adjustment
Fine gain adjustment (pin 1) is provided to compensate for the tolerance of the external coarse gain resistor (Rext) and/or the unavailability of exact coarse gain resistor (Rext) values. Note, the fine gain adjustment will not change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead, the gain of the ADCDS-1403's internal A/D is adjusted allowing the actual input amplifier's full scale VOUT to produce an output code of all ones (11 1111 1111 1111). Fine gain adjustment for the ADCDS-1403 is accomplished using the adjustment circuit shown below (Figure 5). A software controlled D/A converter can be substituted for the 20K: potentiometer. The fine gain adjust circuit ensures that the video input signal (saturated signal) will be properly scaled to obtain the desired Full Scale digital output of 11 1111 1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust should be performed following the offset adjust to avoid interaction. The fine gain adjust provides 256 codes of adjust when 5V supplies are used for the Fine Gain Adjust Circuit.
ADCDS-1403 +5V 20K9 Fine Gain Adjust 1
-5V
Figure 5. Fine Gain Adjustment Circuit
Offset Adjustment vs. External Series Resistor 10000
LSB's of Adjustment
Offset Adjustment Sensitivity External Series Resistor vs. Output Variation (LSB's) 100
Output Variation (LSB's)
1000
10
Peak-Peak variation at potentiometer 100mV
1
100
0.1
10mV
10
0.01
1mV
0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
0
5k
10k 15k
20k 25k
30k 35k
40k 45k
50k
55k 60k
External Series Resistor (Ohm's)
External Series Resistor Value (Ohms)
Figure 6. Offset Adjustment vs. External Series Resistor
Figure 7. Offset Adjustment Sensitivity
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MDA_ADCDS-1403.B01 Page 5 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Out-of-Range Indicator
The ADCDS-1403 provides a digital Out-of-Range output signal (pin 24) for situations when the video input signal (saturated signal) is beyond the input range of the internal A/D converter. The digital output bits and the Out-of-Range signal correspond to a particular sampled video input voltage, with both of these signals having a common pipeline delay. Using the circuit described in Figure 8., both overrange and underrange conditions can be detected (see Table 1). When combined with a D/A converter, digital detection and orrection can be performed for both the gain and offset errors.
Output Coding
The ADCDS-1403's output coding is Straight Binary as indicated in Table 2. The table shows the relationship between the output data coding and the difference between the reference signal voltage and its corresponding video signal voltage. (These voltages are referred to the output of the ADCDS-1403's input amplifier's VOUT).
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates, the ADCDS-1403's input stage must have sufficient analog bandwidth to accurately reproduce the output signals of the CCD array. The amount of analog bandwidth determines how quickly and accurately the "Reference Hold" and the "CDS output" signals will settle. If only a single analog bandwidth was offered, the ADCDS-1403's bandwidth would be set to acquire and digitize CCD output signals to 14-bit accuracy, at maximum conversion rate of 3MHz (333ns see Figure 11. for details). Applications not requiring the maximum conversion rate would be forced to use the full analog bandwidth at the possible expense of noise performance. The ADCDS-1403 avoids this situation by offering a fully programmable analog bandwidth function. The ADCDS-1403 allows the user to "bandwidth limit" the input stage in order to realize the highest level of noise performance for the application being considered. Table 3. describes how to select the appropriate reference hold "aquisition time" and CDS output "settling time" needed for a particular application. Each of the selections listed in Table 3. have been optimized to provide only enough analog bandwidth to acquire a full scale input step, to 14-bit accuracy, in a single conversion. Increasing the analog bandwidth (using a faster settling and acquisition time) would only serve to potentially increase the amount of noise at the ADCDS-1403's output. The ADCDS-1403 uses a two bit digital word to select four different analog bandwidths for the ADCDS-1403's input stage (See Table 3. for details).
MSB "OVERRANGE" OUT-OF-RANGE "UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Table 1. Out-of-Range Conditions OUT OF RANGE 0 0 1 1 MSB 0 1 0 1 OVER RANGE 0 0 0 1 UNDER RANGE 0 0 1 0 INPUT SIGNAL In Range In Range Underrrange Overrange
Table 2. Output Coding INPUT AMPLIFIER VOUT, (VOLTS P-P) Video Signal-Reference Signal > -2.80000 -2.80000 -2.10000 -1.40000 -0.70000 -0.35000 -0.000171 0 Video Signal-Reference Signal
Notes:
SCALE >Full Scale -1LSB Full Scale -1LSB 3/4FS 1/2FS 1/4FS 1/8FS 1 LSB 0 <0
DIGITAL OUTPUT 11 1111 1111 1111 11 1111 1111 1111 11 0000 0000 0000 10 0000 0000 0000 01 0000 0000 0000 00 1000 0000 0000 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000
OUT-OF-RANGE 1 0 0 0 0 0 0 0 1
<0
Input Amplifier VOUT = (Video Signal - Reference Level) The video portion of the differential signal (input-amplifier's VOUT) must be more negative than its associated reference
level and VOUT should not exceed 2.8V DC.
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MDA_ADCDS-1403.B01 Page 6 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Table 3. Programmable Analog Bandwidth REFERENCE HOLD "ACQUISITION TIME" 100ns 200ns 450ns 600ns CDS OUTPUT "SETTLING TIME" 120ns 250ns 500ns 1000ns A0 (PIN 30) 0 1 0 1 A1 (PIN 31) 0 0 1 1 ADCDS-1403 MAXIMUM CONVERSION RATE 3MHz 2MHz 1MHz 0.5MHz -3DB BW 10.5MHz 6.6MHz 3.7MHz 2.5MHz
Note: See Figure 11. for timing details
+12V 4.7F +
+5VD 4.7F +
-5VA 4.7F +
+5VA 4.7F +
0.1F +5V 1 20K -5V +5V 20K -5V External Series Resistor 2 3 4 39
0.1F 36
0.1F 38
0.1F 36 23 BIT 1 (MSB) 22 BIT 2 21 BIT 3 20 BIT 4 19 BIT 5 18 BIT 6 17 BIT 7 16 BIT 8 15 BIT 9 14 BIT 10 13 BIT 11 12 BIT 12 11 BIT 13 10 BIT 14 (LSB)
FINE GAIN ADJUST
ADCDS-1403
OFFSET ADJUST DIRECT INPUT INVERTING INPUT 5 NON-INVERTING INPUT 30 A
0.1F 0.1F
31 A1 25 START CONVERT 26 REF. HOLD 7, 35, 37 ANALOG GROUND
6
+2.4V REFERENCE OUT
24 OUT-OF-RANGE 27 DATA VALID 32, 33 DIGITAL GROUND
Figure 9. ADCDS-1403 Connection Diagram
Timing
The ADCDS-1403 requires two independently operated signals to accurately digitize the analog output signal from the CCD array. * Reference Hold (pin 26) * Start Convert (pin 25) The "Reference Hold" signal controls the operation of an internal sample-hold circuit. A logic "1" places the sample-hold into the hold mode, capturing the value of the CCD's reference signal. The Reference Hold Signal allows the user to control the exact moment when the sample-hold is placed into the "hold" mode. For optimal performance the sample-hold should be placed into the "hold" mode once the reference signal has fully settled from all switching transients to the desired accuracy (user defined). Once the reference signal has been "held" and the video portion of the CCD's analog output signal appears at the ADCDS-1403's input, the ADCDS-1403's correlated double sampler produces a "CDS Output" signal (see Figure 11.) which is the difference between the "held" reference level and its associated video level. When the "CDS Output" signal has settled to the desired accuracy (user defined), the A/D conversion process can be initiated with the rising edge of a single start convert (Pin 25) signal.
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MDA_ADCDS-1403.B01 Page 7 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
Once the A/D conversion has been initiated, Reference Hold (Pin 26) can be placed back into the "Acquisition" mode in order to begin aquiring the next reference level. For optimal performance the ADCDS-1403's internal sample-hold should be placed back into the "Aquisition" mode (Reference Hold to logic "0") during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is defined as the period when the CCD's reference signal has settled from all switching transients to the desired accuracy (see Figure 10.)). Placing the sample-hold back into the "aquisition" mode during the "Reference Quiet Time" prevents the ADCDS-1403's internal amplifiers from unecessarily tracking (reproducing) the large switching transients that occur during the CCD's reset to reference transition.
Reset
Reference "Quiet Time" CCD OUTPUT Reference
Video
100NS MIN.
REFERENCE HOLD
HOLD Acquisition Time Acquisition mode during Reference "Quiet Time" Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1403 should be placed into the Acquisition mode (Reference Hold to logic "0") during the CCD output's Reference "Quiet Time". Reference "Quiet Time" is defined as the period when the reference signal's switching transients have settled to an acceptable (user defined) accuracy.
Figure 10. Reference Hold Timing
Reset N
Reset N+1
Reset N+2
Reset N+3
Reset N+4
CCD OUTPUT
Ref. N Ref N Video N
Ref. N+1 Video N+1
Ref. N+2
Video N+2 Video N+1
Ref. N+3 Video N+3 Video N+1
Ref. N+4
333ns min. 133ns min REFERENCE HOLD IN Hold 120ns min settling line min. settling time
Acquisition Time 100ns min.
Full Scale Step CDS OUTPUT N N+1 150ns typ. min N+2 N+3
START CONVERT
N
N+1
N+2
N+3
DATA VALID
30ns min., 50ns max.
Invalid data DATA OUTPUT DATA N-4 VALID
20ns min max DATA N-3 VALID DATA N-2 VALID DATA N-1 VALID DATA N VALID
Note: As described in Figure 10, the 60ns min. is dependant on the quality of the CCD's Reference when the ADCDS-1403 is switched back into the track mode
Figure 11. ADCDS-1403 Timing Diagram
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MDA_ADCDS-1403.B01 Page 8 of 9
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
(R)
(R)
ADCDS-1403
14-BIT, 3MHz IMAGING SIGNAL PROCESSOR
Made in USA
1.27 TYP. (32.25)
2.24 TYP. (56.90)
0.23 TYP. (5.84)
0.100 TYP. (2.540) 1.900 0.008 (48.260)
0.900 0.010 (22.86)
ORDERING INFORMATION
MODEL OPERATING TEMPERATURE RANGE 40-PIN PACKAGE
ADCDS-1403 ADCDS-1403EX
0 to 70C -55 to 125C
TDIP TDIP
USA: Canada: UK: France: Germany: Japan: China: Singapore:
Mansfield (MA), Tel: (508) 339-3000, email: sales@murata-ps.com Toronto, Tel: (866) 740-1232, email: toronto@murata-ps.com Milton Keynes, Tel: +44 (0)1908 615232, email: mk@murata-ps.com Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: france@murata-ps.com Munchen, Tel: +49 (0)89-544334-0, email: munich@murata-ps.com Tokyo, Tel: 3-3779-1031, email: sales_tokyo@murata-ps.com Osaka, Tel: 6-6354-2025, email: sales_osaka@murata-ps.com Shanghai, Tel: +86 215 027 3678, email: shanghai@murata-ps.com Guangzhou, Tel: +86 208 221 8066, email: guangzhou@murata-ps.com Parkway Centre, Tel: +65 6348 9096, email: singapore@murata-ps.com
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
www.murata-ps.com email: sales@murata-ps.com ISO 9001 and 14001 REGISTERED
03/23/09
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. (c) 2009 Murata Power Solutions, Inc.
www.murata-ps.com
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